Tracing the activity of a data processing system whereby a stream of trace elements is generated representing the step-by-step activity within the data processing system is a highly useful tool in system development. However, with the general move towards more deeply embedded processor cores, it becomes more difficult to track the architectural state of the processor core (such as the contents of registers, the values stored at particular memory locations or the status of various buses, paths, lines, flags or modules within processor core or to which the processor core is coupled) via externally accessible pins. Accordingly, as well as off-chip tracing mechanisms for capturing and analyzing architectural state information, increased amounts of tracing functionality are being placed on-chip. An example of such on-chip tracing mechanisms is the Embedded Trace Macrocell (ETM) provided by ARM Limited, Cambridge, England, in association with various of their ARM processors.
Such tracing mechanisms produce in real time a stream of trace elements representing activities of the data processing system that are desired to be traced. These trace elements can then subsequently be used to facilitate debugging of sequences of processing instructions being executed by the data processing system.
It is known to provide tracing mechanisms incorporating trigger points that serve to control the tracing operation, such as starting or stopping tracing upon access to a particular register, memory address, data value. Such mechanisms are very useful for diagnosing specific parts of a system or types of behavior.
Typically, when the trace is first triggered, the values of all items of architectural state information which may need to be reconstructed are traced. This architectural state information is typically provided from the processor to the ETM over a dedicated input bus. It will be appreciated that the trace bus has a maximum transmission bandwidth which can limit the amount of architectural state information that can be provided to the ETM at any one time.
Typically, the ETM generates a corresponding stream of trace elements representative of the architectural state information which is buffered in a trace buffer prior to output for subsequent analysis. Such a trace buffer is able to store a finite amount of trace elements and requires a dedicated output bus over which the trace elements to be output can be transmitted. The output bus also has a finite bandwidth. The trace buffer is generally arranged to store trace elements in a wrap-around manner, i.e. once the trace buffer is full, new data is typically arranged to overwrite the oldest data stored therein.
Typically, a trace analyzing tool is provided which then receives the trace elements from the trace buffer when desired; e.g. once the trace has completed. The trace analyzing tool can then reconstruct critical components of the architectural state information of the processor core using the stream of trace elements stored in the trace buffer. The trace analyzing tool can therefore reconstruct the behavior of the processor core based on the trace elements.
As data processing systems increase in power and complexity, it is clear that the rate of trace information will increase. Hence, in order to reliably reconstruct the architectural state information it will be appreciated that there is potentially a very large volume of trace elements that need to be generated.
Whilst it is possible to increase the size and performance of the ETM to deal with the increase in data to be processed, it will be appreciated that such increases are undesirable since this results in increased power consumption and is costly in chip area. Furthermore, it is generally desirable to minimize the resources dedicated to ancillary activities such as trace which are not utilized during normal operation of the data processing apparatus.
However, when executing trace, the limitations of the ETM and its infrastructure can result in trace information being lost under certain circumstances.
Debugging effort constitutes a significant cost in the development of new hardware and software systems and losing trace information increases this debugging effort.
Accordingly, it is desired to provide a technique which minimizes the loss of architectural state information being traced.